Instructions
Base Integer Instructions
These base integer instructions are the foundation of the RISC-V architecture.
Loads
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| LB | Load Byte | Y | Y | Y | LB rd,rs1,imm |
| LH | Load Halfword | Y | Y | Y | LH rd,rs1,imm |
| LW | Load Word | Y | Y | Y | LW rd,rs1,imm |
| LD | Load Double | N | Y | Y | LD rd,rs,imm |
| LQ | Load Quad | N | N | Y | LQ rd,rs,imm |
| LBU | Load Byte Unsigned | Y | Y | Y | LBU rd,rs1,imm |
| LHU | Load Halfword Unsigned | Y | Y | Y | LHU rd,rs1,imm |
| LWU | Load Word Unsigned | N | Y | Y | LWU rd,rs1,imm |
| LDU | Load Double Unsigned | N | N | Y | LDU rd,rs1,imm |
Stores
| Instruction | Name | RV32I | R64I | R128I | Syntax |
| SB | Store Byte | Y | Y | Y | SB rs1,rs2,imm |
| SH | Store Halfword | Y | Y | Y | SH rs1,rs2,imm |
| SW | Store Word | Y | Y | Y | SW rs1,rs2,imm |
| SD | Store Double | N | Y | Y | SD rs1,rs2,imm |
| SQ | Store Quad | N | N | Y | SQ rs1,rs2,imm |
Shifts
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| SLL | Shift Left | Y | Y | Y | SLL rd,rs1,rs2 |
| SLLW | Shift Left Word | N | Y | Y | SLLW rd,rs1,rs2 |
| SLLD | Shift Left Double | N | N | Y | SLLD rd,rs1,rs2 |
| SLLI | Shift Left Immediate | Y | Y | Y | SLLI rd,rs1,shamt |
| SLLIW | Shift Left Immediate Word | N | Y | Y | SLLIW rd,rs1,shamt |
| SLLID | Shift Left Immediate Double | N | N | Y | SLLID rd,rs1,shamt |
| SRL | Shift Right | Y | Y | Y | SRL rd,rs1,rs2 |
| SRLW | Shift Right Word | N | Y | Y | SRLW rd,rs1,rs2 |
| SRLD | Shift Right Double | N | N | Y | SRLD rd,rs1,rs2 |
| SRLI | Shift Right Immediate | Y | Y | Y | SRLI rd,rs1,shamt |
| SRLIW | Shift Right Immediate Word | N | Y | Y | SRLIW rd,rs1,shamt |
| SRLID | Shift Right Immediate Double | N | N | Y | SRLID rd,rs1,shamt |
| SRA | Shift Right Arithmetic | Y | Y | Y | SRA rd,rs1,rs2 |
| SRAW | Shift Right Arithmetic Word | N | Y | Y | SRAW rd,rs1,rs2 |
| SRAD | Shift Right Arithmetic Double | N | N | Y | SRAD rd,rs1,rs2 |
| SRAI | Shift Right Arithmetic Imm. | Y | Y | Y | SRAI rd,rs1,shamt |
| SRAIW | Shift Right Arithmetic Imm. Word | N | Y | Y | SRAIW rd,rs1,shamt |
| SRAID | Shift Right Arithmetic Imm. Double | N | N | Y | SRAID rd,rs1,shamt |
Arithmetic
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| ADD | ADD | Y | Y | Y | ADD rd,rs1,rs2 |
| ADDW | ADD Word | N | Y | Y | ADDW rd,rs1,rs2 |
| ADDD | ADD Double | N | N | Y | ADDD rd,rs1,rs2 |
| ADDI | ADD Immediate | Y | Y | Y | ADDI rd,rs1,imm |
| ADDIW | ADD Immediate Word | N | Y | Y | ADDIW rd,rs1,imm |
| ADDID | ADD Immediate Double | N | N | Y | ADDID rd,rs1,imm |
| SUB | Subtract | Y | Y | Y | SUB rd,rs1,rs2 |
| SUBW | Subtract Word | N | Y | Y | SUBW rd,rs1,rs2 |
| SUBD | Subtract Double | N | N | Y | SUBD rd,rs1,rs2 |
| LUI | Load Upper Immediate | Y | Y | Y | LUI rd,imm | |
| AUIPC | Add Upper Imm. to PC | Y | Y | Y | AUIPC rd,imm | |
Logical
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| XOR | XOR | Y | Y | Y | XOR rd,rs1,rs2 |
| XORI | XOR Immediate | Y | Y | Y | XORI rd,rs1,imm |
| OR | OR | Y | Y | Y | OR rd,rs1,rs2 |
| ORI | OR Immediate | Y | Y | Y | ORI rd,rs1,imm |
| AND | AND | Y | Y | Y | AND rd,rs1,rs2 |
| ANDI | AND Immediate | Y | Y | Y | ANDI rd,rs1,imm |
Compare
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| SLT | Set < | Y | Y | Y | SLT rd,rs1,rs2 |
| SLTI | Set < Immediate | Y | Y | Y | SLTI rd,rs1,imm |
| SLTU | Set < Unsigned | Y | Y | Y | SLTU rd,rs1,imm |
| SLTIU | Set < Immediate Unsigned | Y | Y | Y | SLTIU rd,rs1,imm |
Branches
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| BEQ | Branch Equal | Y | Y | Y | BEQ rs1,rs2,imm |
| BNE | Branch Not Equal | Y | Y | Y | BNE rs1,rs2,imm |
| BLT | Branch Less Than | Y | Y | Y | BLT rs1,rs2,imm |
| BGE | Branch Greater Than | Y | Y | Y | BGE rs1,rs2,imm |
| BLTU | Branch Less Than | Y | Y | Y | BLTU rs1,rs2,imm |
| BGEU | Branch Greater Than | Y | Y | Y | BGEU rs1,rs2,imm |
Jump & Link
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| JAL | Jump And Link | Y | Y | Y | JAL rd,imm |
| JALR | Jump And Link Register | Y | Y | Y | JALR rd,rs1,imm |
Sync
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| FENCE | Sync Thread | Y | Y | Y | FENCE |
| FENCE.I | Sync Instruction & Data | Y | Y | Y | FENCE.I |
System
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| SCALL | System CALL | Y | Y | Y | SCALL |
| SBREAK | System BREAK | Y | Y | Y | SBREAK |
Counters
| Instruction | Name | RV32I | RV64I | RV128I | Syntax |
| RDCYCLE | ReaD CYCLE | Y | Y | Y | RDCYCLE rd |
| RDCYCLEH | ReaD CYCLE upper Half | Y | Y | Y | RDCYCLEH rd |
| RDTIME | ReaD TIME | Y | Y | Y | RDTIME rd |
| RDTIMEH | ReaD TIME upper Half | Y | Y | Y | RDTIMEH rd |
| RDINSTRET | ReaD INSTR Retired | Y | Y | Y | RDINSTRET rd |
| RDINSTRETH | ReaD INSTR Retired upper Half | Y | Y | Y | RDINSTRETH rd |
Pseudo-instructions
The RISCV specification also dictates several Pseudo Instructions. These aren't implemented in hardware, but are translated by the assembler to common tasks.
Loads
| Instruction | Name | Actions | RV32I | RV64I | RV128I | Syntax |
| LA | Load Address | AUIPC rd, symbol[31:12]
ADDI rd, rd, symbol[11:0] | Y | Y | Y | LA rd, symbol |
| NOP | No Operation | ADDI x0, x0, 0 | Y | Y | Y | NOP |
| LI | Load Immediate | Varies | Y | Y | Y | LI rd, immediate |
| MV | Move (Copy) Register | ADDI rd, rs, 0 | Y | Y | Y | MV rd, rs |
| SEXT.W | Sign Extend Word | ADDIW rd, rs, 0 | Y | Y | Y | SEXT.W rd, rs |
Branches
| Instruction | Name | Actions | RV32I | RV64I | RV128I | Syntax |
| BEQZ | Branch If Equal Zero | BEQ rs, x0, offset | Y | Y | Y | BEQZ rs, offset |
| BNEZ | Branch If Not Equal Zero | BNE rs, x0, offset | Y | Y | Y | BNEZ rs, offset |
| BLEZ | Branch If Less Than or Equal Zero | BGE x0, rs, offset | Y | Y | Y | BLEZ rs, offset |
| BGEZ | Branch If Greater Than or Equal Zero | BGE x0, rs, offset | Y | Y | Y | BLEZ rs, offset |
| BLTZ | Branch If Less Than Zero | BLT rs, x0, offset | Y | Y | Y | BLTZ rs, offset |
| BGTZ | Branch If Greater Than Zero | BLT x0, rs, offset | Y | Y | Y | BGTZ rs, offset |
| BGT | Branch If Greater Than | BLT rt, rs, offset | Y | Y | Y | BGT rs, rt, offset |
| BLE | Branch If Less Than or Equal | BGE rt, rs, offset | Y | Y | Y | BLE rs, rt, offset |
| BGTU | Branch If Greater Than, Unsigned | BLTU rt, rs, offset | Y | Y | Y | BGTU rs, rt, offset |
| BLEU | Branch If Greater Than or Equal, Unsigned | BGEU rt, rs, offset | Y | Y | Y | BLEU rs, rt, offset |
Compare
| Instruction | Name | Actions | RV32I | RV64I | RV128I | Syntax |
| SEQZ | Set If Equal Zero | SLTIU rd, rs, 1 | Y | Y | Y | SEQZ rd, rs |
| SNEZ | Set If Not Equal Zero | SLTU rd, x0, rs | Y | Y | Y | SNEZ rd, rs |
| SLTZ | Set If Less Than Zero | SLT rd, rs, x0 | Y | Y | Y | SLTZ rd, rs |
| SGTZ | Set If Greater Than Zero | SLT rd, x0, rs | Y | Y | Y | SGTZ rd, rs |
Counters
| Instruction | Name | Actions | RV32I | RV64I | RV128I | Syntax |
| RDCYCLE | Read Cycle Counter | CSRRS rd, cycle[h], x0 | Y | Y | Y | RDCYCLE[h] rd |
| RDTIME | Read Real-Time Clock | CSRRS rd, time[h], x0 | Y | Y | Y | RDTIME[h] rd |
| RDINSTRET | Read Instruction Retired Counter | CSRRS rd, instret[h], x0 | Y | Y | Y | RDINSTRET[h] rd |
Jump & Link
| Instruction | Name | Actions | RV32I | RV64I | RV128I | Syntax |
| J | Jump (Near, Non-returnable) | JAL x0, offset | Y | Y | Y | J offset |
| JAL | Jump And Link (Near, Returnable) | JAL x1, offset | Y | Y | Y | JAL offset |
| JR | Jump Register | JALR x0, rs, 0 | Y | Y | Y | JALR rs |
| JALR | Jump And Link Register | JALR x1, rs, 0 | Y | Y | Y | JALR rs |
| RET | Return From Subroutine | JALR x0, x1, 0 | Y | Y | Y | RET |
| CALL | Call Subroutine (Far, Returnable) | AUIPC x6, offset[31:12]
JALR x1, x6, offset[11:0] | Y | Y | Y | CALL offset |
| TAIL | Tail Call Subroutine (Far, Non-returnable) | AUIPC x6, offset[31:12]
JALR x0, x6, offset[11:0] | Y | Y | Y | TAIL offset |
Logical
| Instruction | Name | Actions | RV32I | RV64I | RV128I | Syntax |
| NOT | One's Complement | XORI rd, rs, -1 | Y | Y | Y | NOT rd, rs |
| NEG | Two's Complement | SUB rd, x0, rs | Y | Y | Y | NEG rd, rs |
| NEGW | Two's Complement Word | SUBW rd, x0, rs | Y | Y | Y | NEGW rd, rs |
Sync
| Instruction | Name | Actions | RV32I | RV64I | RV128I | Syntax |
| FENCE | Fence on all memory and I/O | FENCE iorw, iorw | Y | Y | Y | FENCE |
TODO
| Instruction | Name | Actions | RV32I | RV64I | RV128I | Syntax |
| CSRR | CSR Read | CSRRS rd, csr, x0 | Y | Y | Y | CSRR rd, csr |
| CSRW | CSR Write | CSRRW x0, csr, rs | Y | Y | Y | CSRW csr, rs |
| CSRS | CSR Set Bits | CSRRS x0, csr, rs | Y | Y | Y | CSRS csr, rs |
| CSRC | CSR Clear Bits | CSRRC x0, csr, rs | Y | Y | Y | CSRC csr, rs |
| CSRWI | CSR Write Immediate | CSRRWI x0, csr, imm | Y | Y | Y | CSRWI csr, imm |
| CSRSI | CSR Set Bits Immediate | CSRRSI x0, csr, imm | Y | Y | Y | CSRSI csr, imm |
| CSRCI | CSR Clear Bits Immediate | CSRRCI x0, csr, imm | Y | Y | Y | CSRCI csr, imm |
