an open instruction set architecture
Welcome to risc-v.guru, the easy to read reference manual for the RISC-V Instruction Set Architecture.
This is NOT an official document, but a guide thrown together to allow rapid lookup of assembly instructions for RISC-V. If you're looking for the official source of ISA information, check out the RISC-V foundation.
While this document is as accurate as possible, it should be used as a supplimental reference to the official RISC-V specifications. (Don't depend on this reference for mission critical work)
RISC-V has had multiple important milestones to its adoption. This is a non-exhaustive list of notable events.
- 2010 - RISC-V Specification introduced
- 2017 - Binutils 2.28 was the first version of GNU Binutils with RISC-V support.
- 2017 - GCC 7.1 was the first version of GCC with RISC-V support.
- 2018 - Rust 1.30.0 was the first version of Rust with an RISC-V target (rv32imc)
- 2019 - LLVM 9 was the first version of LLVM with stable RISC-V support.
If you appreciate this site, please consider donating!
- Bitcoin - bc1q0fvhyml7d39a67lt2c8c66q04ad7uzd5mcjfdc
- Eth - 0xA0Ce42789a6e0Baece7B88A6440ce514478Aa0B9
- XLM - GCZ6ZWJQ5TRGX5ISN3U5SMJBIJXEK5G7VEXZ65YHFKRFUWWHBKAGFRCV