The RISC-V ISA is kept minimal to allow for area and energy optimized designs.
While the ISA is kept minimal, modern features are often desired which "bolt on"
These Standard Extensions are well defined within the ISA, and are as follows.
|I||Integer base instructions|
|M||Integer multiplication and division instructions|
|F||Single-precision floating-point instructions|
|D||Double-precision floating-point instructions|
|G||General||(roll-up of I + M + A + F + D above)|
|Q||Quad-precision floating-point instructions|
|L||Decimal floating point instructions|
|B||Bit manipulation instructions|
|J||Dynamically translated languages|
|T||Transactional memory instructions|
|V||Vector operations instructions|
|N||User-level interrupt instructions|
Ordering of the table above must be strictly followed when naming ISA extensions.
- RV64GQLC is valid
- RV64ABCD is not valid
3rd parties are free to implement their own extensions if desired. These are named as follows.
|Xasd||Non-standard User-level extension "asd"|
|SXasd||Non-standard Supervisor-level extension "asd"|
As an example: RV64GQXasd